A field programmable gate array is a chip you can rewire after it leaves the factory. You write code that becomes hardware. An embedded FPGA, or eFPGA, takes that same idea and plants it inside another chip. The programmable logic stops being a separate component and becomes a section of a larger system on chip.

The distinction sounds small. The economics are not. A discrete FPGA sold by the major vendors carries a 65% manufacturer margin, runs hot, and burns board space. Embedding the same programmable fabric into an ASIC cuts the cost by roughly ten times and the power by the same factor, because the power-hungry physical interfaces that a standalone chip needs mostly disappear when the logic lives on the same die as the processor it serves.

What an FPGA Actually Does

To understand eFPGA, you need to understand what an FPGA does differently from a processor.

A CPU runs instructions one at a time. It fetches, decodes, executes, stores. Every operation flows through that pipeline, in sequence, no matter how simple the operation is. A GPU parallelizes this across thousands of cores, but each core is still running an instruction stream.

An FPGA skips the instruction stream entirely. You configure the hardware itself to be the algorithm. A multiply-accumulate operation that takes a CPU several clock cycles to fetch and execute happens in one cycle on an FPGA, because the logic gates are wired to do exactly that. The trade-off has always been flexibility versus efficiency. A CPU can do anything. An FPGA can do one thing very fast, and you can change what that thing is by reloading a configuration file.

The building block is the lookup table, or LUT. A LUT is a small block of memory wired to act as any combinational logic function you need. String enough LUTs together, add memory blocks, add DSP multiply-accumulate units, and connect them all through a grid of switches, and you have an FPGA. Sizes range from 1,000 LUTs for a tiny embedded control task to 500,000 LUTs for heavy signal processing.

The Embedded Difference

A discrete FPGA is a full chip. It has a processor core, memory, the programmable logic fabric, and a ring of physical interfaces, the SerDes and LVDS transceivers that talk to the outside world. That I/O ring is where most of the power goes.

An eFPGA is the fabric without the ring. It is an intellectual property block, or IP core, that a chip designer places inside a larger ASIC or system on chip, where it sits alongside other functional blocks like a USB controller or a memory controller. The programmable logic talks to the rest of the chip over the internal bus, at internal chip speeds, with no physical interface in between.

That changes two things. Cost drops because you are not paying for a separate chip, its package, its margin, or its power-hungry transceivers. Latency drops because data does not have to leave the chip, cross a PCIe bus, enter the FPGA, and come back. The processor and the programmable logic share the same silicon, and the distance between them is measured in microns instead of centimeters.

The major eFPGA IP suppliers report that the cost of the embedded fabric runs about one-tenth the cost of the discrete FPGA it replaces, with the same speed and programmability. Power drops by a similar factor. For a system that needed an FPGA for reconfigurability but could not justify the bulk and heat of a standalone chip, that ratio is the whole argument.

Why the Interconnect Is the Hard Part

The part of an FPGA that is hardest to shrink is not the LUTs. It is the interconnect, the grid of wires and switches that routes signals between logic blocks. In a traditional FPGA mesh interconnect, the routing fabric eats roughly 80% of the chip area. The LUTs and DSP blocks are a minority of the silicon.

That is why eFPGA took decades to arrive. Early attempts in the 1990s stalled because the tooling was thin and the area penalty was steep. The breakthrough came from interconnect architecture. A hierarchical interconnect design that uses roughly half the transistors and half the metal layers of a traditional mesh, while hitting 90% utilization versus 70% for the mesh, is what made eFPGA competitive with discrete FPGAs on density. The same process node now yields roughly the same LUTs per square millimeter whether the fabric is embedded or standalone.

The practical consequence is that eFPGA is no longer a compromise. A chip designer can embed 100,000 LUTs running at 500 megahertz in a 7-nanometer SoC, or embed 1,000 LUTs in a 1-millimeter-square block drawing microwatts. The technology scales across two orders of magnitude in size and four orders of magnitude in power.

The Defense Supply Chain

The part of the eFPGA story that gets less attention in commercial coverage is the reason the Pentagon is interested.

The Department of Defense uses FPGAs heavily across defense systems. The majority of those chips are manufactured in Taiwan. The supply chain risk is the kind of thing that does not matter until it does, and the Pentagon has decided it matters.

eFPGA has been ported to the Sandia National Laboratories 180-nanometer proprietary fab in Albuquerque, to the GlobalFoundries 12LP process in upstate New York, and to the TSMC N5 and N3 nodes being brought up in Arizona. The same programmable fabric that shows up in commercial SoCs can now be built on domestically controlled fabrication lines. For programs that need reconfigurable hardware and cannot accept Taiwan-sourced silicon, that combination is the procurement argument.

Rad-hard variants exist as well. The eFPGA IP can be built using a customer’s own radiation-hardened standard cells, which is how you get programmable logic into satellites and space systems without starting from scratch.

Where the Demand Comes From

The commercial pull on eFPGA comes from places where standards move faster than silicon tape-out cycles.

A 5G base station has to parse packet protocols that are still being revised. An automotive SoC has to support UART and SPI flavors that vary by tier-one supplier. A fintech trading accelerator has to swap its secret-sauce algorithms without leaking them to the chipmaker. A data center network card has to handle new compression and encryption schemes that did not exist when the chip was designed. In all of these cases, the value of reconfiguring the hardware after it ships is high enough to justify the area cost of embedding programmable logic.

The pattern is the same one that made FPGAs a business in the first place. Standards shift, algorithms revise, and hardware, once taped out, stays frozen. eFPGA leaves a patch of thawed ground inside the frozen silicon, which is enough to keep a shipped chip useful across years of changing requirements.

Bringing an advanced finFET SoC to market costs on the order of $50 million. To justify that spend, the chip needs to address a total addressable market in the hundreds of millions. A chip that can be reprogrammed in the field reaches more customers with a single design, because the customer can tailor the programmable block to their own requirements without a metal-mask spin. That widens the market for one tape-out, which is how the area cost of the eFPGA block pays for itself.

The Limits

eFPGA is not free silicon. Clock speeds run lower than a pure standard-cell ASIC implementation of the same logic. Porting existing ASIC RTL into the programmable fabric usually requires some handcrafting, because ASIC designs use gated clocks that FPGAs do not handle well. DSP code has to be shaped to the architecture to hit high utilization. The programmable block adds area, and that area is area you cannot use for fixed functions.

The trade is flexibility now for area and speed. For a chip that will ship in high volume with stable algorithms, that trade is a loss. For a chip that has to survive changing standards, long deployment lifecycles, or customer-specific customization, the trade is the reason the chip exists.

The eFPGA IP suppliers report more than 40 chips licensed and more than 20 already in silicon across nine process nodes, with customers ranging from defense primes to automotive OEMs to microcontroller vendors. The technology is past the experiment phase. The question now is which applications tip into volume first, and the two candidates pulling hardest are edge AI inference and defense reconfigurability. For a pitch running the edge-AI angle through the Gilder publication chain, the George Gilder ambient AI walkthrough covers where embedded programmable fabric sits in that thesis.

Where This Leaves You

If you are reading about eFPGA because a guru named it as the technology behind a teased pick, the honest answer is that the architecture works, the cost and power ratios are documented, and the defense supply chain case is funded, but the specific company is the part you are not getting from the pitch. What the pitch does not tell you is that eFPGA is an intellectual property block licensed to many chipmakers, not a single company’s moat, and that the major FPGA vendors do not see embedded fabric as a threat to their discrete businesses because they serve different problems.

The technology is worth understanding on its own. Whether any single stock captures the value is a separate question, and it is the question the teaser is designed to make you stop asking.

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